1. Field of the Invention
The present invention relates to a photoelectric conversion device, imaging system, and photoelectric conversion device manufacturing method.
2. Description of the Related Art
In a photoelectric conversion device such as a CMOS sensor, element isolation portions are formed in a semiconductor substrate to electrically isolate a plurality of photodiodes.
When STI (Shallow Trench Isolation) element isolation portions are formed in a semiconductor substrate, the space between a plurality of photodiodes can be narrowed. This can reduce, while suppressing a decrease of the area of photodiodes, an area occupied by the unit pixel of the photoelectric conversion device. When forming an STI element isolation portion, a trench is formed in the surface of a semiconductor substrate, and then an oxide film is buried in the trench. The oxide film buried in the trench sometimes applies a stress to the semiconductor substrate.
According to a technique disclosed in Japanese Patent Laid-Open No. 2006-173491, a trench is formed in the surface of a semiconductor substrate, and then a nitride film liner is formed to extend from the bottom and side faces of the trench to the surface of a nitride film on the semiconductor substrate. After that, an oxide film is buried in the trench. According to a technique disclosed in Japanese Patent Laid-Open No. 2006-173491, the nitride film liner can release the stress acting between the bottom faces of the element isolation portion and trench to the surface of the nitride film on the semiconductor substrate, and can thereby relax the stress acting between the bottom faces of the element isolation portion and trench.
To decrease the distance between photodiodes when forming STI element isolation portions in a semiconductor substrate, the element isolation portions need to be formed to a deep region in the semiconductor substrate in order to ensure satisfactory element isolation. In this case, a trench having a high aspect ratio (depth/width) is formed in a semiconductor substrate, and an oxide film is buried in the trench. The oxide film may not be sufficiently filled in the trench. That is, an element isolation portion containing a void near the bottom face may be formed.
According to a technique disclosed in Japanese Patent Laid-Open No. 9-321131, a trench is formed in the surface of a semiconductor substrate, and a silicon nitride film is formed on the bottom and side faces of the trench. Then, only the silicon nitride film on the bottom face is removed. After that, an oxide film is buried in the trench, and then annealing is executed to thermally oxidize the bottom face of the trench. By thermally oxidizing the bottom face of the trench, a thermal oxide film grows to fill a void present near the bottom face of the element isolation portion. According to a technique disclosed in Japanese Patent Laid-Open No. 9-321131, the oxide film can be satisfactorily filled even in a trench having a high aspect ratio. That is, an element isolation portion free from any void can be formed.
According to a technique disclosed in Japanese Patent Laid-Open No. 2002-57318, a trench is formed in the surface of a semiconductor substrate. A P-type impurity, the conductivity type of which is opposite to that of an impurity in a region where charges (electrons) are accumulated in a photodiode, is ion-implanted to the bottom and side faces of the trench. After that, an oxide film is buried in the trench, forming a small channel stop region. According to a technique disclosed in Japanese Patent Laid-Open No. 2002-57318, even when a small element isolation portion is formed by burying an oxide film in a trench having a high aspect ratio (depth/width), satisfactory element isolation can be ensured.
Recently, photoelectric conversion devices require a larger number of pixels in a predetermined chip area. It is necessary to reduce an area occupied by the unit pixel.
As described above, the area occupied by the unit pixel can be reduced by forming an STI element isolation portion in a semiconductor substrate. The number of pixels in a predetermined chip area can be easily increased.